As means for transmitting data at a high speed between a plurality of terminals by way of a data buffer memory, a direct memory access control circuit (hereinafter called a "DMA circuit") has heretofore been known for controlling such transmission. In such a system, when data is to be transferred from a first terminal to a second terminal, a DMA circuit dedicated to the first terminal controls transfer of the data to a prescribed storage area of a buffer memory, and then, another DMA circuit dedicated to the second terminal controls transfer of that data from the buffer memory to the second terminal. This is accomplished with minimum control from the processor in the system thereby permitting the processor to perform other tasks during the data transmission, thereby contributing to a higher system processing speed.
However, where the sector lengths of the transmitting and receiving terminals are different from each other, unless the respective sector lengths are even multiples of one another, the conventional DMA circuits will not be able to transfer all of the data stored in the buffer memory to the receiving terminal in single transmission. Thus, data occupying a fraction of a sector length of the receiving terminal will remain. As a result, in the conventional system, the next data from the transmitting terminal can be transferred to the buffer memory, it has been necessary to first use the processor to shift this remaining data to the beginning of the storage area so that the data can be transferred out of memory in the proper sequence. Of course, such use of the processor naturally reduces the processing speed of the system.